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DP805X
Pipelined High Performance Microcontroller Instructions set details ver 3.10
DP805X Instructions set details
-2Contents
1. 2.
Overview ____________________________________________________________ 6
1.1. Document structure. ________________________________________________________6
Instructions set brief___________________________________________________ 6
2.1. Instruction set notes ________________________________________________________6 2.2. Instruction set brief - functional order _________________________________________7
2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. Arithmetic operations __________________________________________________________ 7 Logic operations ______________________________________________________________ 8 Boolean manipulation __________________________________________________________ 8 Data transfers ________________________________________________________________ 9 Program branches ___________________________________________________________ 10
2.3. Instruction set brief - hexadecimal order ______________________________________11
3.
Instructions set details ________________________________________________ 14
3.1. ACALL __________________________________________________________________14 3.2. ADD_____________________________________________________________________15
3.2.1. 3.2.2. 3.2.3. 3.2.4. 3.3.1. 3.3.2. 3.3.3. 3.3.4. ADD A, Rn _________________________________________________________________ ADD A, direct _______________________________________________________________ ADD A, @Ri ________________________________________________________________ ADD A, #data _______________________________________________________________ ADDC A, Rn ________________________________________________________________ ADDC A, direct ______________________________________________________________ ADDC A, @Ri _______________________________________________________________ ADDC A, #data ______________________________________________________________ 15 15 16 16 17 17 18 18
3.3. ADDC ___________________________________________________________________17
3.4. AJMP____________________________________________________________________19 3.5. ANL _____________________________________________________________________20
3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 3.5.7. 3.5.8. 3.6.1. 3.6.2. 3.6.3. 3.6.4. 3.7.1. 3.7.2. 3.7.3. 3.8.1. 3.8.2. 3.8.3. ANL A, Rn __________________________________________________________________ ANL A, direct________________________________________________________________ ANL A, @Ri ________________________________________________________________ ANL A, #data________________________________________________________________ ANL direct, A________________________________________________________________ ANL direct, #data ____________________________________________________________ ANL C, bit __________________________________________________________________ ANL C, /bit__________________________________________________________________ CJNE A, direct, rel ___________________________________________________________ CJNE A, #data, rel ___________________________________________________________ CJNE RN, #data, rel __________________________________________________________ CJNE @Ri, #data, rel _________________________________________________________ 20 20 21 21 21 21 22 22 23 24 24 25
3.6. CJNE ____________________________________________________________________23
3.7. CLR _____________________________________________________________________26
CLR A _____________________________________________________________________ 26 CLR bit ____________________________________________________________________ 26 CLR C ____________________________________________________________________ 27 CPL A _____________________________________________________________________ 28 CPL bit ____________________________________________________________________ 28 CPL C _____________________________________________________________________ 29
3.8. CPL _____________________________________________________________________28
3.9. DA ______________________________________________________________________30 3.10. DEC ___________________________________________________________________31
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DP805X Instructions set details 3.10.1. 3.10.2. 3.10.3. 3.10.4.
-331 31 32 32
DEC A _____________________________________________________________________ DEC Rn____________________________________________________________________ DEC direct__________________________________________________________________ DEC @Ri __________________________________________________________________
3.11. 3.12.
DIV____________________________________________________________________33 DJNZ __________________________________________________________________34
3.12.1. DJNZ Rn, rel ________________________________________________________________ 34 3.12.2. DJNZ direct, rel ______________________________________________________________ 35
3.13.
INC ___________________________________________________________________36
INC A _____________________________________________________________________ INC Rn ____________________________________________________________________ INC direct __________________________________________________________________ INC @Ri ___________________________________________________________________ INC DPTR __________________________________________________________________ 36 36 37 37 37
3.13.1. 3.13.2. 3.13.3. 3.13.4. 3.13.5.
3.14. 3.15. 3.16. 3.17. 3.18. 3.19. 3.20. 3.21. 3.22. 3.23. 3.24.
JB ____________________________________________________________________38 JBC ___________________________________________________________________39 JC ____________________________________________________________________40 JMP ___________________________________________________________________41 JNB ___________________________________________________________________42 JNC ___________________________________________________________________43 JNZ ___________________________________________________________________44 JZ ____________________________________________________________________45 LCALL_________________________________________________________________46 LJMP __________________________________________________________________47 MOV __________________________________________________________________48
MOV A, Rn _________________________________________________________________ MOV A, direct _______________________________________________________________ MOV A, @Ri ________________________________________________________________ MOV A, #data _______________________________________________________________ MOV Rn, A _________________________________________________________________ MOV Rn, direct ______________________________________________________________ MOV Rn, #data ______________________________________________________________ MOV direct, A _______________________________________________________________ MOV direct, Rn ______________________________________________________________ MOV direct, direct ____________________________________________________________ MOV direct, @Ri _____________________________________________________________ MOV direct, #data ____________________________________________________________ MOV @Ri, A ________________________________________________________________ MOV @Ri, direct _____________________________________________________________ MOV @Ri, #data_____________________________________________________________ MOV C, bit _________________________________________________________________ MOV bit, C _________________________________________________________________ MOV DPTR, #data16 _________________________________________________________ 48 48 49 49 49 49 50 50 50 50 51 51 51 51 52 52 52 53
3.24.1. 3.24.2. 3.24.3. 3.24.4. 3.24.5. 3.24.6. 3.24.7. 3.24.8. 3.24.9. 3.24.10. 3.24.11. 3.24.12. 3.24.13. 3.24.14. 3.24.15. 3.24.16. 3.24.17. 3.24.18.
3.25.
MOVC _________________________________________________________________54
3.25.1. MOVC A, @A + DPTR ________________________________________________________ 54 3.25.2. MOVC A, @A + PC___________________________________________________________ 54
3.26.
MOVX _________________________________________________________________55
3.26.1. MOVX A, @Ri _______________________________________________________________ 55 3.26.2. MOVX A, @DPTR____________________________________________________________ 55 3.26.3. MOVX @Ri, A _______________________________________________________________ 56
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DP805X Instructions set details
-4-
3.26.4. MOVX @DPTR, A____________________________________________________________ 56
3.27. 3.28. 3.29.
MUL___________________________________________________________________57 NOP___________________________________________________________________58 ORL ___________________________________________________________________59
ORL A, Rn__________________________________________________________________ ORL A, direct _______________________________________________________________ ORL A, @Ri ________________________________________________________________ ORL A, #data _______________________________________________________________ ORL direct, A _______________________________________________________________ ORL direct, #data ____________________________________________________________ ORL C, bit __________________________________________________________________ ORL C, /bit _________________________________________________________________ 59 59 60 60 60 60 61 61
3.29.1. 3.29.2. 3.29.3. 3.29.4. 3.29.5. 3.29.6. 3.29.7. 3.29.8.
3.30. 3.31. 3.32. 3.33. 3.34. 3.35. 3.36. 3.37. 3.38.
POP ___________________________________________________________________62 PUSH__________________________________________________________________63 RET ___________________________________________________________________64 RETI __________________________________________________________________65 RL ____________________________________________________________________66 RLC ___________________________________________________________________67 RR ____________________________________________________________________68 RRC___________________________________________________________________69 SETB __________________________________________________________________70
3.38.1. SETB C ____________________________________________________________________ 70 3.38.2. SETB bit ___________________________________________________________________ 70
3.39. 3.40.
SJMP__________________________________________________________________71 SUBB _________________________________________________________________72
SUBB A, Rn ________________________________________________________________ SUBB A, direct ______________________________________________________________ SUBB A, @Ri _______________________________________________________________ SUBB A, #data ______________________________________________________________ 72 72 73 73
3.40.1. 3.40.2. 3.40.3. 3.40.4.
3.41. 3.42.
SWAP _________________________________________________________________74 XCH ___________________________________________________________________75
3.42.1. XCH A, Rn _________________________________________________________________ 75 3.42.2. XCH A, direct _______________________________________________________________ 75 3.42.3. XCH A, @Ri ________________________________________________________________ 75
3.43. 3.44.
XCHD _________________________________________________________________76 XRL ___________________________________________________________________77
XRL A, Rn __________________________________________________________________ XRL A, direct________________________________________________________________ XRL A, @ Ri ________________________________________________________________ XRL A, #data________________________________________________________________ XRL direct, A________________________________________________________________ XRL direct, #data ____________________________________________________________ 77 77 78 78 78 78
3.44.1. 3.44.2. 3.44.3. 3.44.4. 3.44.5. 3.44.6.
4.
Contacts ____________________________________________________________ 79
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DP805X Instructions set details
-5-
Tables Table 1. Notes on data addressing modes_______________________________________ 6 Table 2. Notes on program addressing modes ___________________________________ 6 Table 3. Arithmetic operations ________________________________________________ 7 Table 4. Logic operations ____________________________________________________ 8 Table 5. Boolean manipulation ________________________________________________ 8 Table 6. Data transfer_______________________________________________________ 9 Table 7. Program branches _________________________________________________ 10 Table 8. Instruction set brief in hexadecimal order________________________________ 13
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DP805X Instructions set details
-6-
1. OVERVIEW
1.1. DOCUMENT STRUCTURE.
Document contains brief description of DP805X instructions. This manual is intended for design engineers who are planning to use the DP805X HDL core in conjunction with software assembler, compiler and debugger tools.
2. INSTRUCTIONS SET BRIEF
2.1. INSTRUCTION SET NOTES
The DP805X has five different addressing modes: immediate, direct, register, indirect and relative. In the immediate addressing mode the data is contained in the opcode. By direct addressing an eight bit address is a part of the opcode, by register addressing, a register is selected in the opcode for the operation. In the indirect addressing mode, a register is selected in the opcode to point to the address used by the operation. The relative addressing mode is used for jump instructions. The following tables give a survey about the instruction set cycles of the DP805X microcontroller core. One cycle is equal to one clock period. Table 1 and Table 2 contain notes for mnemonics used in Instruction set tables. Tables 3 7 show instruction hexadecimal codes, number of bytes and machine cycles that each instruction takes to execute.
Rn direct @Ri #data #data16 bit A Working register R0-R7 128 internal RAM locations, any Special Function Registers Indirect internal or external RAM location addressed by register R0 or R1 8-bit constant included in instruction 16-bit constant included as bytes 2 and 3 of instruction 256 software flags, any bit-addressable l/O pin, control or status bit Accumulator
Table 1. Notes on data addressing modes
addr16 addr11 rel Destination address for LCALL and LJMP may be anywhere within the 64-Kbyte of program memory address space. Destination address for ACALL and AJMP will be within the same 2-Kbyte page of program memory as the first byte of the following instruction. SJMP and all conditional jumps include an 8-bit offset byte. Range is +127/-128 bytes relative to the first byte of the following instruction
Table 2. Notes on program addressing modes
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DP805X Instructions set details
-7-
2.2. INSTRUCTION SET BRIEF - FUNCTIONAL ORDER
2.2.1. ARITHMETIC OPERATIONS
Mnemonic
ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,direct SUBB A,@Ri SUBB A,#data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL A,B DIV A,B DA A
Description
Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust accumulator
Code
0x28-0x2F 0x25 0x26-0x27 0x24 0x38-0x3F 0x35 0x36-0x37 0x34 0x98-0x9F 0x95 0x96-0x97 0x94 0x04 0x08-0x0F 0x05 0x06-0x07 0x14 0x18-0x1F 0x15 0x16-0x17 0xA3 0xA4 0x84 0xD4
Bytes Cycles
1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 1 2 1 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 2 3 3 1 2 3 3 1 2 6 3
Table 3. Arithmetic operations
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DP805X Instructions set details
-8-
2.2.2. LOGIC OPERATIONS
Mnemonic
ANL A,Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A
Description
AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator
Code
0x58-0x5F 0x55 0x56-0x57 0x54 0x52 0x53 0x48-0x4F 0x45 0x46-0x47 0x44 0x42 0x43 0x68-0x6F 0x65 0x66-0x67 0x64 0x62 0x63 0xE4 0xF4 0x23 0x33 0x03 0x13 0xC4
Bytes Cycles
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 2 2 3 3 1 2 2 2 3 3 1 2 2 2 3 3 1 1 1 1 1 1 1
Table 4. Logic operations
2.2.3. BOOLEAN MANIPULATION
Mnemonic
CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C
Description
Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit
Code
0xC3 0xC2 0xD3 0xD2 0xB3 0xB2 0x82 0xB0 0x72 0xA0 0xA2 0x92
Bytes Cycles
1 2 1 2 1 2 2 2 2 2 2 2 1 3 1 3 1 3 2 2 2 2 2 3
Table 5. Boolean manipulation
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DP805X Instructions set details
-9-
2.2.4. DATA TRANSFERS
Mnemonic
MOV A,Rn MOV A,direct MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,direct MOV Rn,#data MOV direct,A MOV direct,Rn MOV direct1,direct2 MOV direct,@Ri MOV direct,#data MOV @Ri,A MOV @Ri,direct MOV @Ri,#data MOV DPTR,#data16 MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A
Description
Move register to accumulator Move direct byte to accumulator Move indirect RAM to accumulator Move immediate data to accumulator Move accumulator to register Move direct byte to register Move immediate data to register Move accumulator to direct byte Move register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load data pointer with a 16-bit constant Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A CODE inside ROM/RAM Move A to external destination XRAM data RAM (8-bit address) all other cases CODE inside ROM/RAM Move A to external destination XRAM data RAM (16-bit address) all other cases Push direct byte onto stack Pop direct byte from stack Exchange register with accumulator Exchange direct byte with accumulator Exchange indirect RAM with accumulator Exchange low-order nibble indirect RAM with A
Code
0xE8-0xEF 0xE5 0xE6-0xE7 0x74 0xF8-0xFF 0xA8-0xAF 0x78-0x7F 0xF5 0x88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 E0 F2-F3
Bytes Cycles
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 5* 1 2 2 2 1 3 2 2 2 3 3 3 2 3 2 3 5 4 3* 2* 4*
MOVX @DPTR,A PUSH direct POP direct XCH A,Rn XCH A,direct XCH A,@Ri XCHD A,@Ri
F0 C0 D0 C8-CF C5 C6-C7 D6-D7
1 2 2 1 2 1 1
3* 4* 3 2 2 3 3 3
Table 6. Data transfer
* MOVX cycles depends on STRETCH register. Table shows values with STRETCH=0.
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DP805X Instructions set details
- 10 -
2.2.5. PROGRAM BRANCHES
Mnemonic
ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel JC rel JNC JB bit,rel JNB bit,rel JBC bit,direct rel CJNE A,direct rel CJNE A,#data rel CJNE Rn,#data rel CJNE @Ri,#data rel DJNZ Rn,rel DJNZ direct,rel NOP
Description
Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to reg. and jump if not equal Compare immediate to ind. and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation
Code
0x11-0xF1 03 22 32 01-E1 02 80 73 60 70 40 50 20 30 10 B5 B4 B8-BF B6-B7 D8-DF D5 00
Bytes Cycles
2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 4 4 4 4 3 4 3 5 4 4 3 3 5 5 5 5 4 4 5 4 5 1
Table 7. Program branches
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DP805X Instructions set details
- 11 -
2.3. INSTRUCTION SET BRIEF - HEXADECIMAL ORDER
Opcode 00 H 01 H 02 H 03 H 04 H 05 H 06 H 07 H 08 H 09 H 0A H 0B H 0C H 0D H 0E H 0F H 10 H 11 H 12 H 13 H 14 H 15 H 16 H 17 H 18 H 19 H 1A H 1B H 1C H 1D H 1E H 1F H 20 H 21 H 22 H 23 H 24 H 25 H 26 H 27 H 28 H 29 H 2A H 2B H 2C H 2D H 2E H 2F H Mnemonic NOP AJMP addr11 LJMP addr16 RR A INC A INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 JBC bit,rel ACALL addr11 LCALL addr16 RRC A DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 JB bit.rel AJMP addr11 RET RL A ADD A,#data ADD A,direct ADD A,@R0 ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 Opcode 30 H 31 H 32 H 33 H 34 H 35 H 36 H 37 H 38 H 39 H 3A H 3B H 3C H 3D H 3E H 3F H 40 H 41 H 42 H 43 H 44 H 45 H 46 H 47 H 48 H 49 H 4A H 4B H 4C H 4D H 4E H 4F H 50 H 51 H 52 H 53 H 54 H 55 H 56 H 57 H 58 H 59 H 5A H 5B H 5C H 5D H 5E H 5F H Mnemonic JNB bit.rel ACALL addr11 RETI RLC A ADDC A,#data ADDC A,direct ADDC A,@R0 ADDC A,@R1 ADDC A,R0 ADDC A,R1 ADDC A,R2 ADDC A,R3 ADDC A,R4 ADDC A,R5 ADDC A,R6 ADDC A,R7 JC rel AJMP addr11 ORL direct,A ORL direct,#data ORL A,#data ORL A,direct ORL A,@R0 ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORL A,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORL A,R7 JNC rel ACALL addr11 ANL direct,A ANL direct,#data ANL A,#data ANL A,direct ANL A,@R0 ANL A,@R1 ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7
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DP805X Instructions set details
- 12 Opcode 90 H 91 H 92 H 93 H 94 H 95 H 96 H 97 H 98 H 99 H 9A H 9B H 9C H 9D H 9E H 9F H A0 H A1 H A2 H A3 H A4 H A5 H A6 H A7 H A8 H A9 H AA H AB H AC H AD H AE H AF H B0 H B1 H B2 H B3 H B4 H B5 H B6 H B7 H B8 H B9 H BA H BB H BC H BD H BE H BF H Mnemonic MOV DPTR,#data16 ACALL addr11 MOV bit,C MOVC A,@A+DPTR SUBB A,#data SUBB A,direct SUBB A,@R0 SUBB A,@R1 SUBB A,R0 SUBB A,R1 SUBB A,R2 SUBB A,R3 SUBB A,R4 SUBB A,R5 SUBB A,R6 SUBB A,R7 ORL C,bit AJMP addr11 MOV C,bit INC DPTR MUL AB MOV @R0,direct MOV @R1,direct MOV R0,direct MOV R1,direct MOV R2,direct MOV R3,direct MOV R4,direct MOV R5,direct MOV R6,direct MOV R7,direct ANL C,bit ACALL addr11 CPL bit CPL C CJNE A,#data,rel CJNE A,direct,rel CJNE @R0,#data,rel CJNE @R1,#data,rel CJNE R0,#data,rel CJNE R1,#data,rel CJNE R2,#data,rel CJNE R3,#data,rel CJNE R4,#data,rel CJNE R5,#data,rel CJNE R6,#data,rel CJNE R7,#data,rel
Opcode 60 H 61 H 62 H 63 H 64 H 65 H 66 H 67 H 68 H 69 H 6A H 6B H 6C H 6D H 6E H 6F H 70 H 71 H 72 H 73 H 74 H 75 H 76 H 77 H 78 H 79 H 7A H 7B H 7C H 7D H 7E H 7F H 80 H 81 H 82 H 83 H 84 H 85 H 86 H 87 H 88 H 89 H 8A H 8B H 8C H 8D H 8E H 8F H
Mnemonic JZ rel AJMP addr11 XRL direct,A XRL direct,#data XRL A,#data XRL A,direct XRL A,@R0 XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 JNZ rel ACALL addr11 ORL C,direct JMP @A+DPTR MOV A,#data MOV direct,#data MOV @R0,#data MOV @R1,#data MOV R0.#data MOV R1.#data MOV R2.#data MOV R3.#data MOV R4.#data MOV R5.#data MOV R6.#data MOV R7.#data SJMP rel AJMP addr11 ANL C,bit MOVC A,@A+PC DIV AB MOV direct,direct MOV direct,@R0 MOV direct,@R1 MOV direct,R0 MOV direct,R1 MOV direct,R2 MOV direct,R3 MOV direct,R4 MOV direct,R5 MOV direct,R6 MOV direct,R7
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DP805X Instructions set details
- 13 Opcode E0 H E1 H E2 H E3 H E4 H E5 H E6 H E7 H E8 H E9 H EA H EB H EC H ED H EE H EF H F0 H F1 H F2 H F3 H F4 H F5 H F6 H F7 H F8 H F9 H FA H FB H FC H FD H FE H FF H Mnemonic MOVX A,@DPTR AJMP addr11 MOVX A,@R0 MOVX A,@R1 CLR A MOV A, direct MOV A,@R0 MOV A,@R1 MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 MOVX @DPTR,A ACALL addr11 MOVX @R0,A MOVX @R1,A CPL A MOV direct, A MOV @R0,A MOV @R1,A MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A
Opcode C0 H C1 H C2 H C3 H C4 H C5 H C6 H C7 H C8 H C9 H CA H CB H CC H CD H CE H CF H D0 H D1 H D2 H D3 H D4 H D5 H D6 H D7 H D8 H D9 H DA H DB H DC H DD H DE H DF H
Mnemonic PUSH direct AJMP addr11 CLR bit CLR C SWAP A XCH A, direct XCH A,@R0 XCH A,@R1 XCH A,R0 XCH A,R1 XCH A,R2 XCH A,R3 XCH A,R4 XCH A,R5 XCH A,R6 XCH A,R7 POP direct ACALL addr11 SETB bit SETB C DA A DJNZ direct, rel XCHD A,@R0 XCHD A,@R1 DJNZ R0,rel DJNZ R1,rel DJNZ R2,rel DJNZ R3,rel DJNZ R4,rel DJNZ R5,rel DJNZ R6,rel DJNZ R7,rel
Table 8. Instruction set brief in hexadecimal order
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DP805X Instructions set details
- 14 -
3. INSTRUCTIONS SET DETAILS
3.1.
ACALL
ACALL addr11 Absolute call ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, op code bits 7-5, and the second byte of the instruction. The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL. No flags are affected. (PC) (SP) ((SP)) (SP) ((SP)) (PC10-0) 2 4 (PC) + 2 (SP) + 1 (PC7-0) (SP) + 1 (PC15-8) page address
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
a10 a9
a8
1
0
0
0
1
a7
a6
a5
a4
a3
a2
a1
a0
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DP805X Instructions set details
- 15 -
3.2.
ADD
ADD A, Adds A to the source operand and returns the result to A. ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register- indirect, or immediate.
Instruction: Function: Description:
3.2.1. ADD A, RN Operation: (PC) (PC) + 1 (A) (A) + (Rn) 1 1
Bytes: Cycles: Encoding:
0
0
1
0
1
r
r
r
3.2.2. ADD A, DIRECT Operation: (PC) (PC) + 2 (A) (A) + (direct) 2 2
Bytes: Cycles: Encoding:
0
0
1
0
0
1
0
1
direct address
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DP805X Instructions set details
- 16 -
3.2.3. ADD A, @RI Operation: (PC) (PC) + 1 (A) (A) + ((Ri)) 1 2
Bytes: Cycles: Encoding:
0
0
1
0
0
1
1
i
3.2.4. ADD A, #DATA Operation: (PC) (PC) + 2 (A) (A) + #data 2 2
Bytes: Cycles: Encoding:
0
0
1
0
0
1
0
0
immediate data
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DP805X Instructions set details
- 17 -
3.3.
ADDC
ADDC A, < src-byte> Adds A and the source operand, then adds one (1) if CY is set, and puts the result in A. ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand-addressing modes are allowed: register= direct, registerindirect, or immediate.
Instruction: Function:
Description:
3.3.1. ADDC A, RN Operation: (PC) (PC) + 1 (A) (A) + (C) + (Rn) 1 1
Bytes: Cycles: Encoding:
0
0
1
1
1
r
r
r
3.3.2. ADDC A, DIRECT Operation: (PC) (PC) + 2 (A) (A) + (C) + (direct) 2 2
Bytes: Cycles: Encoding:
0
0
1
1
0
1
0
1
direct address
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DP805X Instructions set details
- 18 -
3.3.3. ADDC A, @RI Operation: (PC) (PC) + 1 (A) (A) + (C) + ((Ri)) 1 2
Bytes: Cycles: Encoding:
0
0
1
1
0
1
1
i
3.3.4. ADDC A, #DATA Operation: (PC) (PC) + 2 (A) (A) + (C) + #data 2 2
Bytes: Cycles: Encoding:
0
0
1
1
0
1
0
0
immediate data
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DP805X Instructions set details
- 19 -
3.4.
AJMP
AJMP addr11 Absolute jump AJMP transfers program execution to the indicated address, which is formed at run- time by concatenating the high-order five bits of the PC (after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP. (PC) (PC) + 2 (PC10-0) page address 2 3
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
a10 a9
a8
0
0
0
0
1
a7
a6
a5
a4
a3
a2
a1
a0
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DP805X Instructions set details
- 20 -
3.5.
ANL
ANL , Logical AND for byte operands ANL performs the bit wise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected (except P, if = A). The two operands allow six addressing mode combinations. When the destination is a accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Instruction: Function: Description:
Note:
3.5.1. ANL A, RN Operation: (PC) (PC) + 1 (A) (A) and (Rn) 1 1
Bytes: Cycles: Encoding:
0
1
0
1
1
r
r
r
3.5.2. ANL A, DIRECT Operation: (PC) (PC) + 2 (A) (A) and (direct) 2 2
Bytes: Cycles: Encoding:
0
1
0
1
0
1
0
1
direct address
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DP805X Instructions set details
- 21 -
3.5.3. ANL A, @RI Operation: (PC) (PC) + 1 (A) (A) and ((Ri)) 1 2
Bytes: Cycles: Encoding:
0
1
0
1
0
1
1
i
3.5.4. ANL A, #DATA Operation: (PC) (PC) + 2 (A) (A) and #data 2 2
Bytes: Cycles: Encoding:
0
1
0
1
0
1
0
0
immediate data
3.5.5. ANL DIRECT, A Operation: (PC) (PC) + 2 (direct) (direct) and (A) 2 3
Bytes: Cycles: Encoding:
0
1
0
1
0
0
1
0
direct address
3.5.6. ANL DIRECT, #DATA Operation: (PC) (PC) + 3 (direct) (direct) and #data 3 3
Bytes: Cycles: Encoding:
0
1
0 1 0 0 direct address immediate data
1
1
Instruction:
ANL C,
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DP805X Instructions set details
- 22 -
Function: Description:
Logical AND for bit operands If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash ("/" preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct bit addressing is allowed for the source operand.
3.5.7. ANL C, BIT Operation: (PC) (PC) + 2 (C) (C) and (bit) 2 2
Bytes: Cycles: Encoding:
1
0
0
0
0
0
1
0
bit address
3.5.8. ANL C, /BIT Operation: (PC) (PC) + 2 (C) (C) and / (bit) 2 2
Bytes: Cycles: Encoding:
1
0
1
1
0
0
0
0
bit address
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DP805X Instructions set details
- 23 -
3.6.
CJNE
CJNE , < src-byte >, rel Compare and jump if not equal. CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.
Instruction: Function: Description:
3.6.1. CJNE A, DIRECT, REL Operation: (PC) (PC) + 3 if (A) < > (direct) then (PC) (PC) + relative offset if (A) < (direct) then (C) 1 else (C) 0 Bytes: Cycles: Encoding:
1 0 1 1 0 1 direct address relative address 0 1
3 5
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DP805X Instructions set details
- 24 -
3.6.2. CJNE A, #DATA, REL Operation: (PC) (PC) + 3 if (A) < > data then (PC) (PC) + relative offset if (A) < data then (C) 1 else (C) 0 Bytes: Cycles: Encoding:
1 0 1 1 0 1 immediate data relative address 0 0
3 4
3.6.3. CJNE RN, #DATA, REL Operation: (PC) (PC) + 3 if (Rn) < > data then (PC) (PC) + relative offset if (Rn) < data then (C) 1 else (C) 0 Bytes: Cycles: Encoding:
1 0 1 1 1 r immediate data relative address r r
3 4
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DP805X Instructions set details
- 25 -
3.6.4. CJNE @RI, #DATA, REL Operation: (PC) (PC) + 3 if ((Ri)) < > data then (PC) (PC) + relative offset if ((Ri)) < data then (C) 1 else (C) 0 Bytes: Cycles: Encoding:
1 0 1 1 0 1 immediate data relative address 1 i
3 5
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DP805X Instructions set details
- 26 -
3.7.
CLR
3.7.1. CLR A Function: Clear accumulator
Description: The accumulator is cleared (all bits set to zero). No flags are affected. Operation: (PC) (PC) + 1 (A) 0 1 1
Bytes: Cycles: Encoding:
1
1
1
0
0
1
0
0
3.7.2. CLR Function:
BIT
Clear bit
Description: The indicated bit is cleared (reset to zero). No other flags are affected. Operation: (PC) (PC) + 2 bit 0 2 3
Bytes: Cycles: Encoding:
1
1
0
0
0
0
1
0
bit address
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DP805X Instructions set details
- 27 -
3.7.3. CLR C Function: Clear carry
Description: The carry flag is cleared (reset to zero). No other flags are affected. Operation: (PC) (PC) + 1 (C) 0 1 1
Bytes: Cycles: Encoding:
1
1
0
0
0
0
1
1
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DP805X Instructions set details
- 28 -
3.8.
CPL
3.8.1. CPL A Function: Complement accumulator
Description: Each bit of the accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to zero and vice versa. No flags are affected. Operation: (PC) (PC) + 1 (A) / (A) 1 1
Bytes: Cycles: Encoding:
1
1
1
1
0
1
0
0
3.8.2. CPL BIT Function: Complement bit
Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data will be read from the output data latch, not the input pin. (PC) (PC) + 2 (C) (bit) 2 3
Operation:
Bytes: Cycles: Encoding:
1
0
1
1
0
0
1
0
bit address
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DP805X Instructions set details
- 29 -
3.8.3. CPL C Function: Complement carry
Description: The carry flag is complemented. A bit which had been a one is changed to zero and vice versa. Operation: (PC) (PC) + 1 (C) / (C) 1 1
Bytes: Cycles: Encoding:
1
0
1
1
0
0
1
1
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DP805X Instructions set details
- 30 -
3.9.
DA
DA A Decimal adjust accumulator for addition DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the low- order nibble. This internal addition would set the carry flag if a carry-out of the loworder four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially; this instruction performs the decimal conversion by adding 00 H , 06 H , 60 H , or 66 H to the accumulator, depending on initial accumulator and PSW conditions. DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation, nor does DA A apply to decimal subtraction. (PC) (PC) + 1 if [[(A3-0) > 9] ^ [(AC) = 1]] then (A3-0) (A3-0) + 6 next if [[(A7-4) > 9] ^ [(C) = 1]] then (A7-4) (A7-4) + 6 1 3
Instruction: Function: Description:
Note:
Operation:
Bytes: Cycles: Encoding:
1
1
0
1
0
1
0
0
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DP805X Instructions set details
- 31 -
3.10.
DEC
DEC byte Decrement byte The variable indicated is decremented by 1. An original value of 00 H will underflow to 0FF H. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Instruction: Function: Description:
Note:
3.10.1. Operation:
DEC A (PC) (PC) + 1 (A) (A) - 1 1 1
Bytes: Cycles: Encoding:
0
0
0
1
0
1
0
0
3.10.2. Operation:
DEC RN (PC) (PC) + 1 (Rn) (Rn) - 1 1 2
Bytes: Cycles: Encoding:
0
0
0
1
1
r
r
r
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DP805X Instructions set details
- 32 -
3.10.3. Operation:
DEC DIRECT (PC) (PC) + 2 (direct) (direct) - 1 2 3
Bytes: Cycles: Encoding:
0
0
0
1
0
1
0
1
direct address
3.10.4. Operation:
DEC @RI (PC) (PC) + 1 ((Ri)) ((Ri)) - 1 1 3
Bytes: Cycles: Encoding:
0
0
0
1
0
1
1
i
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DP805X Instructions set details
- 33 -
3.11.
DIV
DIV AB Divide DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared. If B had originally contained 00 H, the values returned in the accumulator and B register will be undefined and the overflow flag will be set. The carry flag is cleared in any case. (PC) (PC) + 1 (A15-8) (A) / (B) - result's bits 15..8 (B7-0) (A) / (B) - result's bits 7..0 1 6
Instruction: Function: Description:
Exception:
Operation:
Bytes: Cycles: Encoding:
1
0
0
0
0
1
0
0
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DP805X Instructions set details
- 34 -
3.12.
DJNZ
DJNZ , Decrement and jump if not zero DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00 H will underflow to 0FF H. No flags are affected. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Instruction: Function: Description:
Note:
3.12.1. Operation:
DJNZ RN, REL (PC) (PC) + 2 (Rn) (Rn) - 1 if (Rn) 0 then (PC) (PC) + rel 2 4
Bytes: Cycles: Encoding:
1
1
0
1
1
r
r
r
relative address
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DP805X Instructions set details
- 35 -
3.12.2. Operation:
DJNZ DIRECT, REL (PC) (PC) + 3 (direct) (direct) - 1 if (direct) 0 then (PC) (PC) + rel 3 5
Bytes: Cycles: Encoding:
1
1
0
1 0 1 0 direct address relative address
1
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DP805X Instructions set details
- 36 -
3.13.
INC
INC operand Increment INC increments the indicated variable by 1. An original value of 0FFh will overflow to 00h. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. INC A (PC) (PC) + 1 (A) (A) + 1 1 1
Instruction: Function: Description:
Note:
3.13.1. Operation:
Bytes: Cycles: Encoding:
0
0
0
0
0
1
0
0
3.13.2. Operation:
INC RN (PC) (PC) + 1 (Rn) (Rn) + 1 1 2
Bytes: Cycles: Encoding:
0
0
0
0
1
r
r
r
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DP805X Instructions set details
- 37 -
3.13.3. Operation:
INC DIRECT (PC) (PC) + 2 (direct) (direct) + 1 2 3
Bytes: Cycles: Encoding:
0
0
0
0
0
1
0
1
direct address
3.13.4. Operation:
INC @RI (PC) (PC) + 1 ((Ri)) ((Ri)) + 1 1 3
Bytes: Cycles: Encoding:
0
0
0
0
0
1
1
i
3.13.5. Function:
INC DPTR Increment data pointer
Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00 H will increment the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Operation: (PC) (PC) + 1 (DPTR) (DPTR) + 1 1 1
Bytes: Cycles: Encoding:
1
0
1
0
0
0
1
1
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DP805X Instructions set details
- 38 -
3.14.
JB
JB bit, rel Jump if bit is set If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. (PC) (PC) + 3 if (bit) = 1 then (PC) (PC) + rel 3 5
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
1
0 0 0 0 bit address relative address
0
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DP805X Instructions set details
- 39 -
3.15.
JBC
JBC bit, rel Jump if bit is set and clear bit If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. (PC) (PC) + 3 if (bit) = 1 then (bit) 0 (PC) (PC) + rel 3 5
Instruction: Function: Description:
Note:
Operation:
Bytes: Cycles: Encoding:
0
0
0
1 0 0 0 bit address relative address
0
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DP805X Instructions set details
- 40 -
3.16.
JC
JC rel Jump if carry is set If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative- displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. (PC) (PC) + 2 if (C) = 1 then (PC) (PC) + rel 2 3
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
1
0
0
0
0
0
0
relative address
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DP805X Instructions set details
- 41 -
3.17.
JMP
JMP @A + DPTR Jump indirect Add the eight-bit unsigned contents of the accumulator with the sixteenbit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the accumulator nor the data pointer is altered. No flags are affected. (PC) (A) + (DPTR) 1 5
Instruction: Function: Description:
Operation: Bytes: Cycles: Encoding:
0
1
1
1
0
0
1
1
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DP805X Instructions set details
- 42 -
3.18.
JNB
JNB bit,rel Jump if bit is not set If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. (PC) (PC) + 3 if (bit) = 0 then (PC) (PC) + rel. 3 5
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
1
1 0 0 0 bit address relative address
0
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DP805X Instructions set details
- 43 -
3.19.
JNC
JNC rel Jump if carry is not set If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. (PC) (PC) + 2 if (C) = 0 then (PC) (PC) + rel 2 3
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
1
0
1
0
0
0
0
relative address
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DP805X Instructions set details
- 44 -
3.20.
JNZ
JNZ rel Jump if accumulator is not zero If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected. (PC) (PC) + 2 if (A) 0 then (PC) (PC) + rel. 2 4
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
1
1
1
0
0
0
0
relative address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 45 -
3.21.
JZ
JZ rel Jump if accumulator is zero If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected. (PC) (PC) + 2 if (A) = 0 then (PC) (PC) + rel 2 4
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
1
1
0
0
0
0
0
relative address
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 46 -
3.22.
LCALL
LCALL addr16 Long call LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space. No flags are affected. (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (PC15-8) (PC) addr15-0 3 4
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
0
1 0 0 address 15..8 address 7..0
1
0
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 47 -
3.23.
LJMP
LCALL addr16 Long jump LJMP causes an unconditional branch to the indicated address, by loading the high- order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected. (PC) addr15... addr0 3 4
Instruction: Function: Description:
Operation: Bytes: Cycles: Encoding:
0
0
0
0 0 0 address 15..8 address 7..0
1
0
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 48 -
3.24.
MOV
MOV , Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed. MOV A, RN (PC) (PC) + 1 (A) (Rn) 1 1
Instruction: Function: Description:
3.24.1. Operation:
Bytes: Cycles: Encoding:
1
1
1
0
1
r
r
r
3.24.2. Operation:
MOV A, DIRECT (PC) (PC) + 2 (A) (direct) MOV A, ACC is a valid instruction. 2 2
Note: Bytes: Cycles: Encoding:
1
1
1
0
0
1
0
1
direct address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 49 -
3.24.3. Operation:
MOV A, @RI (PC) (PC) + 1 (A) ((Ri)) 1 2
Bytes: Cycles: Encoding:
1
1
1
0
0
1
1
i
3.24.4. Operation:
MOV A, #DATA (PC) (PC) + 2 (A) #data 2 2
Bytes: Cycles: Encoding:
0
1
1
1
0
1
0
0
immediate data
3.24.5. Operation:
MOV RN, A (PC) (PC) + 1 (Rn) (A) 1 1
Bytes: Cycles: Encoding:
1
1
1
1
1
r
r
r
3.24.6. Operation:
MOV RN, DIRECT (PC) (PC) + 2 (Rn) (direct) 2 3
Bytes: Cycles: Encoding:
1
0
1
0
1
r
r
r
direct address
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http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 50 -
3.24.7. Operation:
MOV RN, #DATA (PC) (PC) + 2 (Rn) #data 2 2
Bytes: Cycles: Encoding:
0
1
1
1
1
r
r
r
immediate data
3.24.8. Operation:
MOV DIRECT, A (PC) (PC) + 2 (direct) (A) 2 2
Bytes: Cycles: Encoding:
1
1
1
1
0
1
0
1
direct address
3.24.9. Operation:
MOV DIRECT, RN (PC) (PC) + 2 (direct) (Rn) 2 2
Bytes: Cycles: Encoding:
1
0
0
0
1
r
r
r
direct address
3.24.10. Operation:
MOV DIRECT, DIRECT (PC) (PC) + 3 (direct) (direct) 3 3
Bytes: Cycles: Encoding:
1
0
0 0 0 1 0 1 direct address (source) direct address (destination)
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 51 -
3.24.11. Operation:
MOV DIRECT, @RI (PC) (PC) + 2 (direct) ((Ri)) 2 3
Bytes: Cycles: Encoding:
1
0
0
0
0
1
1
i
direct address
3.24.12. Operation:
MOV DIRECT, #DATA (PC) (PC) + 2 (direct) #data 3 3
Bytes: Cycles: Encoding:
0
1
1 1 0 1 0 direct address (source) immediate data
1
3.24.13. Operation:
MOV @RI, A (PC) (PC) + 1 ((Ri)) (A) 1 2
Bytes: Cycles: Encoding:
1
1
1
1
0
1
1
i
3.24.14. Operation:
MOV @RI, DIRECT (PC) (PC) + 2 ((Ri)) (direct) 2 3
Bytes: Cycles: Encoding:
1
0
1
0
0
1
1
i
direct address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 52 -
3.24.15. Operation:
MOV @RI, #DATA (PC) (PC) + 2 ((Ri)) #data 2 2
Bytes: Cycles: Encoding:
0
1
1
1
0
1
1
i
immediate data
3.24.16. Function:
MOV C, BIT Move bit data
Description: The Boolean variable indicated by the second operand (directly addressable bit) is copied into carry flag. No other register or flag is affected. Operation: (PC) (PC) + 2 (C) (bit) 2 2
Bytes: Cycles: Encoding:
1
0
1
0
0
0
1
0
bit address
3.24.17. Function:
MOV BIT, C Move carry flag
Description: The carry flag is copied into the Boolean variable indicated by the first operand (directly addressable bit). No other register or flag is affected. Operation: (PC) (PC) + 2 (bit) (C) 2 3
Bytes: Cycles: Encoding:
1
0
0
1
0
0
1
0
bit address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 53 -
3.24.18. Function:
MOV DPTR, #DATA16 Load data pointer with a 16-bit constant
Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once. Operation: (PC) (PC) + 3 DPH immediate data15...8 DPL immediate data7..0 3 3
Bytes: Cycles: Encoding:
1
0
0 0 0 1 0 immediate data 15...8 immediate data 7...0
1
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 54 -
3.25.
MOVC
MOVC A, @A + Move code byte The MOVC instructions load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added to the accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. MOVC A, @A + DPTR (PC) (PC) + 1 (A) ((A) + (DPTR)) 1 5
Instruction: Function: Description:
3.25.1. Operation:
Bytes: Cycles: Encoding:
1
0
0
1
0
0
1
1
3.25.2. Operation:
MOVC A, @A + PC (PC) (PC) + 1 (A) ((A) + (PC)) 1 4
Bytes: Cycles: Encoding:
1
0
0
0
0
0
1
1
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 55 -
3.26.
MOVX
MOVX , Move external The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the X appended to MOV. There are two types of instructions, differing in whether they provide an eightbit or sixteen-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provides an eight-bit address, in the second type of MOVX instructions, the data pointer generates a sixteen-bit address. MOVX A, @RI (PC) (PC) + 1 (A) ((Ri)) 1 3*
Instruction: Function: Description:
3.26.1. Operation:
Bytes: Cycles: Encoding:
1
1
1
0
0
0
1
i
3.26.2. Operation:
MOVX A, @DPTR (PC) (PC) + 1 (A) ((DPTR)) 1 2*
Bytes: Cycles: Encoding:
1
1
1
0
0
0
0
0
* MOVX cycles depends on STRETCH register. Shown values with STRETCH=0.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 56 -
3.26.3. Operation:
MOVX @RI, A (PC) (PC) + 1 ((Ri)) (A) 1 4* - if MOVX CODE is executed from on-chip ROM or on-chip RAM, and destination data are placed inside off-chip XRAM 5* - for all other cases as follow: CODE inside off-chip XPRG, destination inside off-chip XRAM CODE inside off-chip XPRG, destination inside off-chip XPRG CODE inside off-chip XPRG, destination inside on-chip PRG RAM CODE inside on-chip ROM, destination inside off-chip XPRG CODE inside on-chip ROM, destination inside on-chip PRG RAM CODE inside on-chip RAM, destination inside off-chip XPRG CODE inside on-chip RAM, destination inside on-chip PRG RAM
Bytes: Cycles:
Encoding:
1 1 1 1 0 0 1 i
3.26.4. Operation:
MOVX @DPTR, A (PC) (PC) + 1 ((DPTR)) (A) 1 3* - if MOVX CODE is executed from on-chip ROM or on-chip RAM, and destination data are placed inside off-chip XRAM 4* - for all other cases as listed above
Bytes: Cycles:
Encoding:
1 1 1 1 0 0 0 0
* MOVX cycles depends on STRETCH register. Shown values with STRETCH=0.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 57 -
3.27.
MUL
MUL AB Multiply MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FF H) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. (PC) (PC) + 1 (A) (A) x (B) - result's bits 7..0 (B) (A) x (B) - result's bits 15..8
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
1 2
1
0
1
0
0
1
0
0
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 58 -
3.28.
NOP
No operation Execution continues at the following instruction. Other than the PC, no registers or flags are affected. (PC) (PC) + 1 1 1
Function: Description:
Operation: Bytes: Cycles: Encoding:
0
0
0
0
0
0
0
0
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 59 -
3.29.
ORL
ORL , Logical OR for byte variables ORL performs the bit wise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected (except P, if = A). The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. ORL A, RN (PC) (PC) + 1 (A) (A) or (Rn) 1 1
Instruction: Function: Description:
Note:
3.29.1. Operation:
Bytes: Cycles: Encoding:
0
1
0
0
1
r
r
r
3.29.2. Operation:
ORL A, DIRECT (PC) (PC) + 2 (A) (A) or (direct) 2 2
Bytes: Cycles: Encoding:
0
1
0
0
0
1
0
1
direct address
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http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 60 -
3.29.3. Operation:
ORL A, @RI (PC) (PC) + 1 (A) (A) or ((Ri)) 1 2
Bytes: Cycles: Encoding:
0
1
0
0
0
1
1
i
3.29.4. Operation:
ORL A, #DATA (PC) (PC) + 1 (A) (A) or #data 2 2
Bytes: Cycles: Encoding:
0
1
0
0
0
1
0
0
immediate data
3.29.5. Operation:
ORL DIRECT, A (PC) (PC) + 1 (direct) (direct) or (A) 2 3
Bytes: Cycles: Encoding:
0
1
0
0
0
0
1
0
direct address
3.29.6. Operation:
ORL DIRECT, #DATA (PC) (PC) + 1 (direct) (direct) or #data 3 3
Bytes: Cycles: Encoding:
0
1
0
0 0 0 1 direct address Immediate data
1
Instruction:
ORL C,
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 61 -
Function: Description:
Logical OR for bit variables Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state otherwise. A slash ("/") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. ORL C, BIT (PC) (PC) + 2 (C) (C) or (bit) 2 2
3.29.7. Operation:
Bytes: Cycles: Encoding:
0
1
1
1
0
0
1
0
bit address
3.29.8. Operation:
ORL C, /BIT (PC) (PC) + 2 (C) (C) or /(bit) 2 2
Bytes: Cycles: Encoding:
1
0
1
0
0
0
0
0
bit address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 62 -
3.30.
POP
POP direct Pop from stack The contents of the internal RAM location addressed by the stack pointer are read, and the stack pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated. No flags are affected. (PC) (PC) + 2 (direct) ((SP)) (SP) (SP) - 1 2 2
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
1
1
0
1
0
0
0
0
direct address
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 63 -
3.31.
PUSH
PUSH direct Push onto stack The stack pointer is incremented by one. The contents of the indicated variable are then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected. (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (direct) 2 3
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
1
1
0
0
0
0
0
0
direct address
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 64 -
3.32.
RET
Return from subroutine RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. (PC15-8) (SP) (PC7-0) (SP) 1 4 ((SP)) (SP) - 1 ((SP)) (SP) - 1
Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
1
0
0
0
1
0
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 65 -
3.33.
RETI
Return from interrupt RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower or same-level interrupt is pending when the RETI instruction is executed, that one instruction will be executed before the pending interrupt is processed. (PC15-8) (SP) (PC7-0) (SP) 1 4 ((SP)) (SP) - 1 ((SP)) (SP) - 1
Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
1
1
0
0
1
0
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 66 -
3.34.
RL
RL A Rotate accumulator left The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. (PC) (PC) + 1 (An + 1) (An) n = 0-6 (A0) (A7) 1 1
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
1
0
0
0
1
1
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 67 -
3.35.
RLC
RLC A Rotate accumulator left through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected. (PC) (An + 1) (A0) (C) 1 1 (PC) + 1 (An) n = 0-6 (C) (A7)
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
1
1
0
0
1
1
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 68 -
3.36.
RR
RR A Rotate accumulator right The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. (PC) (PC) + 1 (An) (An + 1) n = 0-6 (A7) (A0) 1 1
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
0
0
0
0
1
1
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 69 -
3.37.
RRC
RRC A Rotate accumulator right through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected. (PC) (An) (A7) (C) 1 1 (PC) + 1 (An + 1) n=0-6 (C) (A0)
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
0
0
0
1
0
0
1
1
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 70 -
3.38.
SETB
SETB Set bit SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. SETB C (PC) (PC) + 1 (C) 1 1 1
Instruction: Function: Description:
3.38.1. Operation:
Bytes: Cycles: Encoding:
1
1
0
1
0
0
1
1
3.38.2. Operation:
SETB BIT (PC) (PC) + 2 (bit) 1 2 3
Bytes: Cycles: Encoding:
1
1
0
1
0
0
1
0
bit address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 71 -
3.39.
SJMP
SJMP rel Short jump Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. Under the above conditions the instruction following SJMP will be at 102 H. Therefore, the displacement byte of the instruction will be the relative offset (0123 H - 0102 H ) = 21 H . In other words, an SJMP with a displacement of 0FE H would be a one-instruction infinite loop. (PC) (PC) + 2 (PC) (PC) + rel 2 3
Instruction: Function: Description:
Note:
Operation:
Bytes: Cycles: Encoding:
1
0
0
0
0
0
0
0
relative address
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 72 -
3.40.
SUBB
SUBB A, Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand). AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register-indirect, or immediate. SUBB A, RN (PC) (PC) + 1 (A) (A) - (C) - (Rn) 1 1
Instruction: Function: Description:
3.40.1. Operation:
Bytes: Cycles: Encoding:
1
0
0
1
1
r
r
r
3.40.2. Operation:
SUBB A, DIRECT (PC) (PC) + 2 (A) (A) - (C) - (direct) 2 2
Bytes: Cycles: Encoding:
1
0
0
1
0
1
0
1
direct address
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 73 -
3.40.3. Operation:
SUBB A, @RI (PC) (PC) + 1 (A) (A) - (C) - ((Ri)) 1 2
Bytes: Cycles: Encoding:
1
0
0
1
0
1
1
i
3.40.4. Operation:
SUBB A, #DATA (PC) (PC) + 2 (A) (A) - (C) - #data 2 2
Bytes: Cycles: Encoding:
1
0
0
1
0
1
0
0
immediate data
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 74 -
3.41.
SWAP
SWAP A Swap nibbles within the accumulator SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No flags are affected. (PC) (PC) + 1 (A3-0) (A7-4), (A7-4) (A3-0) 1 1
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
1
1
0
0
0
1
0
0
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http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 75 -
3.42.
XCH
XCH A, Exchange accumulator with byte variable XCH loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing. XCH A, RN (PC) (PC) + 1 (A) (Rn) 1 2
Instruction: Function: Description:
3.42.1. Operation:
Bytes: Cycles: Encoding:
1
1
0
0
1
r
r
r
3.42.2. Operation:
XCH A, DIRECT (PC) (PC) + 2 (A) (direct) 2 3
Bytes: Cycles: Encoding:
1
1
0
0
0
1
0
1
direct address
3.42.3. Operation:
XCH A, @RI (PC) (PC) + 1 (A) ((Ri)) 1 3
Bytes: Cycles: Encoding:
1
1
0
0
0
1
1
i
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http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 76 -
3.43.
XCHD
XCHD A, @Ri Exchange digit XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or BCD digit), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. (PC) (PC) + 1 (A3-0) ((Ri)3-0) 1 3
Instruction: Function: Description:
Operation:
Bytes: Cycles: Encoding:
1
1
0
1
0
1
1
i
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 77 -
3.44.
XRL
XRL , Logical Exclusive OR for byte variables XRL performs the bit wise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected (except P, if = A). The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be accumulator or immediate data. When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. XRL A, RN (PC) (PC) + 1 (A) (A) xor (Rn) 1 1
Instruction: Function: Description:
Note:
3.44.1. Operation:
Bytes: Cycles: Encoding:
0
1
1
0
1
r
r
r
3.44.2. Operation:
XRL A, DIRECT (PC) (PC) + 2 (A) (A) xor (direct) 2 2
Bytes: Cycles: Encoding:
0
1
1
0
0
1
0
1
direct address
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 78 -
3.44.3. Operation:
XRL A, @ RI (PC) (PC) + 1 (A) (A) xor ((Ri)) 1 2
Bytes: Cycles: Encoding:
0
1
1
0
0
1
1
i
3.44.4. Operation:
XRL A, #DATA (PC) (PC) + 2 (A) (A) xor #data 2 2
Bytes: Cycles: Encoding:
0
1
1
0
0
1
0
0
immediate data
3.44.5. Operation:
XRL DIRECT, A (PC) (PC) + 2 (direct) (direct) xor (A) 2 3
Bytes: Cycles: Encoding:
0
1
1
0
0
0
1
0
direct address
3.44.6. Operation:
XRL DIRECT, #DATA (PC) (direct) 3 3 (PC) + 3 (direct) xor #data
Bytes: Cycles: Encoding:
0
1
1
0 0 0 1 direct address immediate data
1
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DP805X Instructions set details
- 79 -
4. CONTACTS
If any problems are encountered please contact Digital Core Design. Headquarters: Wroclawska 94 41-902 Bytom POLAND e-mail: iinffo@dcd..pll n o@dcd p tel. fax : +48 32 282 82 66 : +48 32 282 74 37
Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinffoUS@dcd..pll n oUS@dcd p tel. fax : +1 210 422 8268 : +1 210 679 7511
Distributors: Please check httttp::////www..dcd..pll//aparrttn..php h p www dcd p apa n php
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.

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